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RSP 2024 Program

 

The proceedings can be downloaded through this secured link. Access credentials will be provided during the event to the registered attendees.

Room/Location: Hannover III

09:00 am - 10:00 am  Session 1 Crypto - Session Chair: Tobias Strauch, R&D, EDAptix e.K.

• Muhammad Awais, Maria Mushtaq, Lirida Naviner, Florent Bruguier, Jawad Haj Yahya and Pascal Benoit
  Decoding Attack Behaviors by Analyzing Patterns in Instruction-Based Attacks using gem5

• Yakir Forman and William Harrison
  Temporal Staging for Correct-by-Construction Cryptographic Hardware 

10:00 am - 10:30 am    Coffee break

10:30 am - 12:30 pm  Session 2 Hardware - Session Chair: Kenneth Kent, University of New Brunswick

• Ka Chuen Cheng, Umair F. Siddiqi, Gary Grewal, and Shawki M. Areibi
  Invited talk: Circuit Partitioning with Reinforcement Learning and Edge-Based Initialization

• Rim Zrelli, Henrique Amaral Misson, Maroua Ben Attia, Felipe Gohring de Magalhaes, Abdo Shabah and Gabriela Nicolescu
  Advancing Formal Verification: Fine-Tuning LLMs for Translating Natural Language Requirements to CTL Specifications

• Tobias Strauch
  Transaction Level Hierarchy Guided and Functional Coverage Driven Deductive Formal Verification

• Pawan Kumar and Hokeun Kim
  Cost-Effective Cyber-Physical System Prototype for Precision Agriculture with a Focus on Crop Growth

12:30 pm - 01:30 pm    Lunch break

01:30 pm - 03:00 pm  Keynote (co-located with TCRS Workshop)

• Claire Pagetti, Senior research scientist, ONERA
  Certification of (hybrid) multi-core architectures

03:00 pm - 03:30 pm    Coffee break

03:30 pm - 5:00 pm  Session 3 Synthesis Flow and Performance Evaluation - Session Chair: Felipe Gohring de Magalhaes, Polytechnique Montreal

• Tobias Strauch
  Non-interfering On-line and In-field SoC Testing

• Eduardo Tomasi Ribeiro, César Fuguet, Christian Fabre and Frédéric Pétrot
  Page size exploration for RISC-V systems: the case for HPC

• Navid Jafarof and Kenneth Kent
  Enhancing the VTR Flow: Integration of ABC9 via Yosys for Better Technology Mapping and Optimization

 

5:00 pm  - End of Workshop

 

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Keynote, co-located with TCRS Workshop, Certification of (hybrid) multi-core architectures

Claire Pagetti, Senior research scientist, ONERA

Abstract: Multi-core processors have been available for many years on the market and they have been consequently embedded in safety-critical systems (e.g. automotive domain) for more than a decade. They have yet to break through in the avionic domain, one subject to certification. To allow the use of new technologies in a system, the applicant to certification must ensure safety properties and in particular its compliance with certification standards. The A(M)C AMC20-152A and AMC20-193 (formally CAST 32A) define objectives for the respective certification of hardware platforms and of multi-core processors. The PHYLOG project (2016 - 2020) proposed a methodology to facilitate the certification of multi-core processors in the avionic domain. Among the project outcomes, we will present the formal language PML that helps identify interferences within processors, and a stressing benchmarks methodology to help quantify the impact of said interferences.
Multi-core processors certification is now a reality and many applicants are working towards their certification. The emergence of Deep Neural Network (DNN) and machine learning-based applications paved the way for a new generation of hybrid hardware platforms. Hybrid platforms embed several cores and hardware accelerators in a small package. PHYLOG 2, as a follow up of PHYLOG, aims to prepare for the certification of these new platforms. We will present the advancement of the PHYLOG methodology extension for them.

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