RSP 2020 Program
Rapid System Prototyping is be part of ESWEEK'20 and is held this year as a virtual event through Whova platform, as the other associated ESWEEK events.
Pre-recorded video presentations and PDF versions of each paper will be available through Whova before the workshop. Attendees will be able to post questions to authors or upvote existing questions in the Q&A forums of each paper provided within Whova.
In addition, live technical sessions are proposed on Thursday (Sept 24). These sessions will be short due to the constraint of different time zones. The authors will present an overview of their papers in 3-minute lightning talks at the beginning of the live session. The remainder of the session is dedicated to live Q&A between authors and attendees, including questions previously posted in the Q&A forums as moderated by the Session Chairs.
Note that attendees have access to all associated ESWEEK events!
Indicated time is in Central European Summer Time (CEST) zone
14:15 - 14:30 Welcome - Opening Remarks
14:30 - 15:00 Keynote
- Prof. Sungjoo Yoo, Seoul National University, Quantizing neural networks for ultra-low-precision computation
15:00 - 15:30 Live technical session A - Session Chair: Sungjoo Yoo, Seoul National University
-
Erwan Moreac, El Mehdi Abdali, Francois Berry, Dominique Heller and Jean-Philippe Diguet.
Hardware-in-the-loop simulation with dynamic partial FPGA reconfiguration applied to computer vision in ROS-based UAV -
Daniel Gis, Nils Büscher and Christian Haubelt.
Advanced Debugging Architecture for Smart Inertial Sensors using Sensor-in-the-Loop -
Erwan Lenormand, Thierry Goubier, Loïc Cudennec and Henri-Pierre Charles.
A combined fast/cycle accurate simulation tool for reconfigurable accelerator evaluation: application to distributed data management
15:30 - 15:40 Break
15:40 - 16:10 Live technical session B - Session Chair: Kenneth Kent, University of New Brunswick
-
Chen Wu, Virginie Fresse, Benoit Suffran and Hubert Konik.
Mathematic models based on multiple-criteria decision analysis for tuning industrial CNN in an FPGA computing cluster -
José Domingues, Fábio Coutinho, Samuel Pereira, Pedro Marques, Hugerles Silva and Arnaldo Oliveira.
Fast MPSoC Prototyping of a Reconfigurable DU Downlink Transmission Chain for 5G New Radio -
Jeremy Nadal and Amer Baghdadi.
FPGA based design and prototyping of efficient 5G QC-LDPC channel decoding
16:10 - 16:20 Break
16:20 - 16:50 Live technical session C - Session Chair: Amer Baghdadi, IMT Atlantique/Lab-STICC
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Jean Bruant, Pierre-Henri Horrein, Olivier Muller, Tristan Groléat and Frédéric Pétrot.
(System)Verilog to Chisel Translation for Faster Hardware Design -
Xuzhi Zhang, Narendra Prabhu and Russell Tessier.
NestedNet: A Container-based Prototyping Tool for Hierarchical Software Defined Networks -
Seyed Alireza Damghani, Jean-Philippe Legault and Kenneth B. Kent.
Desired Footprint by Technology Mapping Modification using a Genetic Algorithm in Odin II
16:50 - 17:00 Break - End of Workshop
Keynote
Sungjoo Yoo (Seoul National University), "Quantizing neural networks for ultra-low-precision computation"
Bit-width needs to be minimized for efficient neural network design in terms of chip area, code size, and, most importantly, energy efficiency. In this talk, we first review state-of-the-art quantization methods in the industry and academia and introduce our ideas of outlier quantization, precision highway and quantization error fluctuation-aware training, which finally offers 4-bit linear weight/activation quantization of MobileNet v3.